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Analogue Front End for an FPGA-Based DLS System
Analogue front-end design, low-noise signal conditioning, dynamic light scattering
Low-noise analogue front end for a compact DLS system, designed to condition photodetector signals ahead of FPGA-based acquisition and correlation.
This project focuses on the analogue front end for a compact Dynamic Light Scattering (DLS) system. The board conditions the photodetector output through low-noise filtering, gain staging, and stable power regulation so the downstream digital system can sample a clean, reliable scattered-light signal.
The design includes a buck-boost supply that generates a regulated 5 V rail across a range of input voltages, helping protect measurement quality from supply variation and transients. The PCB was laid out in Altium Designer with deliberate separation between the power, analogue, and digital domains to preserve signal integrity. The current revision includes the full schematic, routed PCB, and bill of materials, forming the analogue foundation for a later FPGA-based acquisition and correlation stage.
Highlights
- Low-noise analogue front end for photodetector signal conditioning
- Filtering, gain staging, and stable power tailored for DLS measurements
- Buck-boost power stage providing a regulated 5 V rail
- Ground plane separation across power, analogue, and digital domains
What Matters
- Altium Designer
- Low-noise analogue design
- Buck-boost converter
- Analogue signal conditioning
- Photodetector interface
- SMD PCB layout